1. Field of the Invention
The present invention relates to a Triple Gate(Tri-gate) device, and more particularly, to a three dimensional transistor device having a three-sided strained-Si channel and its manufacturing method.
2. Description of the Prior Art
Transistors are the miniscule on/off switches that make up the integrated circuits in today's microprocessors. Three dimensional (3D) vertical double-gate transistors are known in the art. Chipmakers keep announcing that they have fabricated the smallest vertical double-gate transistors reported to date using industry standard technology. These transistors, measuring below ten nanometers, or ten billionths of a meter in length (gate), are about six times smaller than the smallest transistors currently in production.
A double-gate transistor structure effectively doubles the electrical current that can be sent through a given transistor. The Fin Field Effect Transistor (FinFET) design relies upon a thin vertical silicon “fin” to help control leakage of current through the transistor when it is in the “off” stage. Moreover, while the gate length is shrunk to bellow 65 nm, the wrapped-around gate upon the very thin Si-fin body can provide excellent gate control capability for effectively suppressing short channel effect through the fully depleted silicon-on-insulator (SOI) operation mode. The superior leakage control characteristics and excellent gate control for effectively suppressing short channel effect make FinFET transistors an attractive candidate for future nano-scale CMOS generations, which are expected to be in manufacturing within the next decade.
Typically, FinFET is built on a silicon-on-insulator (SOI) substrate. The silicon layer of the SOI substrate is etched into “fin” like shaped body of the transistor. The gate is wrapped around and over the fin.
U.S. Pat. No. 4,996,574 filed Jun. 30, 1989 by Shirasaki, entitled “MIS transistor structure for increasing conductance between source and drain regions” discloses a metal-insulator-semiconductor transistor comprising an insulator layer, a silicon body provided on the insulator layer and comprising a source region, a drain region and a channel region extending in a first direction between and interconnecting the source region and the drain region, a gate insulator film provided on the silicon body so as to cover the channel region except for the part of the channel region in contact with the insulator layer, and a gate electrode of a conductive material provided in contact with the gate insulator film so as to cover the channel region underneath the gate insulator film except for the part of the channel region in contact with the insulator layer.
U.S. Pat. No. 5,338,959 filed Mar. 30, 1993 by Kim et al. discloses a thin film transistor gate structure with a three-dimensional multi-channel structure. The thin film transistor gate structure comprises source/drain electrodes formed so as to be spaced from and opposite to each other on a substrate. The TFT has a plurality of channel regions for high carrier mobility. Each channel region has three-dimensional structure. The polycrystalline silicon channel regions are surrounded by gates.
U.S. Pat. No. 6,413,802 filed on Oct. 23, 2000 by Hu et al. discloses a FinFET device that is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity.
However the electrical performance such as carrier mobility or device driving current of the above-described SOI-based FinFET and Tri-gate devices can be further improved.